The present invention relates to the design of semiconductor integrated circuits, and more specifically to reduction of ramp time violations during a placement-based re-synthesis procedure, prior to routing.
Semiconductor integrated circuits are traditionally designed and fabricated by first preparing a schematic diagram or hardware description language (HDL) specification of a logical circuit in which functional elements are interconnected to perform a particular logical function. With standard cell technology, the schematic diagram or HDL specification is synthesized into standard cells of a specific cell library or into generic cells that are later re-synthesized into cells of a specific cell library.
Each cell corresponds to a logical function unit, which is implemented by one or more transistors that are optimized for the cell. The logic designer selects the cells according to the number of loads that are attached to the cell, as well as an estimated interconnection required for routing. The cells in the cell library are defined by cell library definitions. Each cell library definition includes cell layout definitions and cell characteristics. The cell layout definition includes a layout pattern of the transistors in the cell, geometry data for the cell""s transistors and cell routing data. The cell characteristics include, for example, a cell propagation delay, a model of the cell""s function, input capacitance, output capacitance and output ramp time as a function of load.
A series of computer-aided design tools generate a netlist from the schematic diagram or HDL specification of the selected cells and the interconnections between the cells. The netlist is used by a floor planner or placement tool to place the selected cells at particular locations in an integrated circuit layout pattern. The interconnections between the cells are then routed along predetermined routing layers. The design tools then determine the output loading of each cell as a function of the number of loads attached to each cell, the placement of each cell and the routed interconnections.
A timing analysis tool is then used to identify timing violations within the circuit. The time it takes for a signal to travel along a particular path or xe2x80x9cnetxe2x80x9d from one sequential element to another depends on the number of cells in the path, the internal cell delay, the number of loads attached to the cells in the path, the length of the routed interconnections in the path and the drive strengths of the transistors in the path. Once any timing violations have been corrected, the netlist, the cell layout definitions, the placement data and the routing data together form an integrated circuit layout definition, which can be used to fabricate the integrated circuit.
In a traditional iterative design process, timing violations are eliminated by making adjustments at each stage in the layout process. For example, an under-driven cell may be fixed by changing the logic diagram or logic synthesis tool to insert a cell having a larger drive strength. Alternatively, the logic diagram can be changed to divide the loads between one or more redundant cells or buffer cells. An exceptionally long routing path can be corrected by adjusting the routing path itself and/or the placement of cells in the path.
Until recently, there has been little interaction between the various computer-aided design tools because the above steps were well-defined and there was not a great need for interaction. However, the current movement toward the use of deep-sub-micron technology will fundamentally alter this methodology, and increased interaction between logic synthesis and layout is becoming necessary. For example, placement-driven synthesis uses information available after placement to make decisions about logic transformations. These logic transformations can include the re-synthesis of generic cells into cells of a specific technology library or when optimizing areas of the logic design that contain large, multi-input functional blocks, such as large AND, OR and XOR blocks and large buffer trees having multiple xe2x80x9cfanoutsxe2x80x9d. These blocks can be implemented with a variety of circuit configurations. The placement information is used to achieve timing closure during these logic transformations, which can avoid numerous time consuming iterations.
However, prior to routing, there is little timing information on which to base these timing closure decisions. These decisions are based on only rough timing estimates of the delay through each logical function and typical routing path lengths. This is particularly true when the logic design is being synthesized into generic cells, as opposed to cells of a particular cell library or technology. In the typical approach, the initial placement is not timing driven since little or no timing information is available at this stage in the fabrication process.
For example, the logic transformation decisions during re-synthesis do not take into account ramp time violations. The ramp time of a signal is the time it takes a device to drive a net from a logic low state to a logic high state. Each technology has a specified maximum allowable ramp time that can occur at the input of a cell. As a particular signal propagates through the interconnected cells, degradation of ramp times along the interconnect causes the signal waveform to change shape. This change in waveform shape not only increases critical path delay, but also makes it difficult to estimate ramp times at the inputs of the driven cells. These ramp time estimates are important factors in calculating delays of the next stages and consequently, in calculating critical path delay and clock frequency. In addition, waveform deformation can be so extensive as to exceed the maximum allowable ramp time at the input of a cell, which causes a ramp time violation. This is particularly true with deep sub-micron technology. All such violation must be eliminated prior to finalizing the integrated circuit layout definition used for fabrication.
Once routing information is available, it is possible to precisely calculate the waveform shape at the inputs of the driven cells and to find ramp time degradations and violations. For example, L. Pillage and R. Rohrer, xe2x80x9cAsymptotic Waveform Evaluation for Timing Analysisxe2x80x9d, IEEE Trans. on Computer-Aided Design, 352-366, (April 1990) describe an algorithm commonly used for that purpose. It would, however, be of great benefit to be able to estimate and eliminate ramp time violations early in the design process because the lower level design processes tools such as routing have not been capable of changing the netlist structure and have limited options for violation elimination. Unfortunately, there are several obstacles to estimating and eliminating ramp time violations prior to routing. These obstacles include unavailability of exact wire lengths and interconnect topology, inaccurate interconnect models and ramp time estimations used in synthesis and placement, and unavailability of an efficient algorithm to eliminate ramp time violations based on available information. Most existing design tools cannot handle these problems.
Thus, improved techniques are desired for estimating an eliminating ramp time violations earlier in the design process, such as during placement-based logic resynthesis.
One aspect of the present invention relates to a method of generating constraints for an integrated circuit logic re-synthesis algorithm. According to the method, a netlist of interconnected logic elements is received, which includes a plurality of nets, wherein each of the nets is coupled between a respective net driver logic element and at least one driven logic element. Also received are a maximum allowable input ramp time specification for the logic elements and an output ramp time specification for the net driver logic elements. A maximum interconnect capacitance constraint is then generated for each of the net driver logic elements based on the output ramp time specification for that net driver logic element and the maximum allowable input ramp time specification.
Another aspect of the present invention is directed to a computer-readable medium having instructions readable by a computer-aided design tool for optimizing a functional block within a netlist of an integrated circuit. The instructions, when executed, cause the tool to perform steps, including (a) inputting the netlist, wherein the netlist comprises interconnected logic elements, including a plurality of nets, wherein each of the nets is coupled between a respective net driver logic element and at least one driven logic element; (b) inputting a maximum allowable input ramp time specification for the logic elements and an output ramp time specification for the net driver logic elements; and (c) generating a maximum interconnect capacitance constraint for each of the net driver logic elements based on the output ramp time specification for that net driver logic element and the maximum allowable input ramp time specification.
Another aspect of the present invention is directed to a computer-aided design tool for optimizing a functional block within a netlist of interconnected logic elements, which includes a plurality of nets. Each of the nets is coupled between a respective net driver logic element and at least one driven logic element. The design tool receives the netlist, a maximum allowable input ramp time specification for the logic elements, and an output ramp time specification for the net driver logic elements. The design tool then generates a maximum interconnect capacitance constraint for each of the net driver logic elements based on the output ramp time specification for that net driver logic element and the maximum allowable input ramp time specification.